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STK16CA8
128K x 8 AutoStorePlusTM nvSRAM QuantumTrapTM CMOS Nonvolatile Static RAM Preliminary
FEATURES
* 25ns, 35ns and 45ns Access Times * Directly Replaces 128K x 8 Static RAM, Battery-Backed RAM or EEPROM * Transparent Data Save on Power Down * STORE to QuantumTrapTM Nonvolatile Elements is Initiated by Software or AutoStorePlusTMon Power Down * RECALL to SRAM Initiated by Software or Power Restore * 5mA Typical ICC at 200ns Cycle Time * Unlimited READ and WRITE Cycles to SRAM * 100-Year Data Retention to Quantum Trap * Single 3V +20%, -10% Operation * Commercial and Industrial Temperatures * 32-Pin DIP Package
DESCRIPTION
The Simtek STK16CA8 is a fast static RAM with a nonvolatile element in each static memory cell. The embedded nonvolatile elements incorporate Simtek's QuantumTrapTM technology producing the world's most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent, nonvolatile data resides in the nonvolatile elements. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) can take place automatically on power down or under software control. An internal capacitor guarantees the STORE operation, even under extreme power-down slew rates or loss of power from "hot swapping". Transfers from the nonvolatile elements to the SRAM (the RECALL operation) take place automatically on restoration of power. Initiation of STORE and RECALL cycles can also be controlled by entering control sequences on the SRAM inputs. The STK16CA8 is pin-compatible with 128k x 8 SRAMs and batterybacked SRAMs, allowing direct substitution while providing superior performance.
BLOCK DIAGRAM
VCC Quantum Trap 1024 x 1024
ROW DECODER
PIN CONFIGURATIONS
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A5 A6 A7 A8 A9 A12 A13 A14 A15 A16
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
POWER CONTROL
STORE STATIC RAM ARRAY 1024 x 1024 RECALL STORE/ RECALL CONTROL
VCC A15 NC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
INPUT BUFFERS
COLUMN I/O COLUMN DEC
SOFTWARE DETECT
A0 - A15
PIN NAMES
A0 - A16 W DQ0 - DQ7 Address Inputs Write Enable Data In/Out Chip Enable Output Enable Power (+ 3V) Ground
A0 A1 A2 A3 A4 A10 A11
G E W
E G VCC VSS
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ABSOLUTE MAXIMUM RATINGSa
Power Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +3.9V Voltage on Input Relative to VSS . . . . . . . . . .-0.5V to (VCC + 0.5V) Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . .-0.5V to (VCC + 0.5V) Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .-55C to 125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to 150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
Note a: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC CHARACTERISTICS
SYMBOL ICC b
1
(VCC = 3.0V +20%, -10%)
COMMERCIAL MIN MAX 50 40 35 1.5 5 1 1 1 2.0 VSS - .5 2.4 0.4 0 70 - 40 VCC + .3 0.8 2.0 VSS - .5 2.4 0.4 85 INDUSTRIAL MIN MAX 55 45 35 1.5 5 1 1 1 VCC + .3 0.8 UNITS mA mA mA mA mA mA A A V V V V C tAVAV = 25ns tAVAV = 35ns tAVAV = 45ns All Inputs Don't Care, VCC = max W (V CC - 0.2V) All Others Cycling, CMOS Levels E (V CC - 0.2V) All Others VIN 0.2V or (VCC - 0.2V) VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G VIH All Inputs All Inputs IOUT = - 2mA IOUT = 4mA NOTES
PARAMETER Average VCC Current
ICC c
2 3
Average VCC Current during STORE Average VCC Current at tAVAV = 200ns 3V, 25C, Typical VCC Standby Current (Standby, Stable CMOS Input Levels) Input Leakage Current Off-State Output Leakage Current Input Logic "1" Voltage Input Logic "0" Voltage Output Logic "1" Voltage Output Logic "0" Voltage Operating Temperature
ICC b ISBd IILK IOLK VIH VIL VOH VOL TA
Note b: ICC and ICC are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. 1 3 Note c: ICC is the average current required for the duration of the STORE cycle (tSTORE ) . 2 Note d: E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
CAPACITANCEe
SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance
(TA = 25C, f = 1.0MHz)
MAX 5 7 UNITS pF pF CONDITIONS V = 0 to 3V V = 0 to 3V
3.0V
577 Ohms OUTPUT 789 Ohms 30 pF INCLUDING SCOPE AND FIXTURE
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
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SRAM READ CYCLES #1 & #2
NO. 1 2 3 4 5 6 7 8 9 10 11 SYMBOLS #1, #2 tELQV tAVAVf tAVQVg tGLQV tAXQXg tELQX tEHQZh tGLQX tGHQZh tELICCHe tEHICCLe Alt. tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS PARAMETER Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold after Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby 0 25 0 10 0 35 3 3 10 0 13 0 45 25 25 10 3 3 13 0 15 STK16CA8-25 MIN MAX 25 35 35 15 3 3 15
(VCC = 3.0V +20%, -10%)
STK16CA8-35 MIN MAX 35 45 45 20 STK16CA8-45 MIN MAX 45 UNITS ns ns ns ns ns ns ns ns ns ns ns
Note f: W must be high during SRAM READ cycles. Note g: Device is continuously selected with E and G both low. Note h: Measured 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledf, g
2 tAVAV ADDRESS 5 tAXQX DQ (DATA OUT) 3 tAVQV
DATA VALID
SRAM READ CYCLE #2: E Controlledf
2 tAVAV ADDRESS 6 1 tELQV 1 1 tEHICCL 7 tEHQZ
E
tELQX
G 8 4 tGLQV
9 tGHQZ
tGLQX DQ (DATA OUT)
DATA VALID
tELICCH
ACTIVE
10
ICC
STANDBY
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SRAM WRITE CYCLES #1 & #2
NO. 12 13 14 15 16 17 18 19 20 21 SYMBOLS #1 tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX t WLQZ h, i tWHQX #2 tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX Alt. tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Set-up to End of Write Data Hold after End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold after End of Write Write Enable to Output Disable Output Active after End of Write 3 PARAMETER MIN 25 20 20 10 0 20 0 0 10 3
(VCC = 3.0V +20%, -10%)
STK16CA8-25 MAX STK16CA8-35 MIN 35 25 25 12 0 25 0 0 13 3 MAX STK16CA8-45 MIN 45 30 30 15 0 30 0 0 15 MAX UNITS ns ns ns ns ns ns ns ns ns ns
Note i: Note j:
If W is low when E goes low, the outputs remain in the high-impedance state. E or W must be VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledj
12 tAVAV ADDRESS 14 tELWH E 17 tAVWH 13 tWLWH 15 tDVWH DATA IN 20 tWLQZ DATA OUT
PREVIOUS DATA HIGH IMPEDANCE DATA VALID
19 tWHAX
tAVWL W
18
16 tWHDX
21 tWHQX
SRAM WRITE CYCLE #2: E Controlledj
12 tAVAV ADDRESS 18 tAVEL E 14 tELEH 19 tEHAX
17 tAVEH W
13 tWLEH 15 tDVEH 16 tEHDX
DATA VALID HIGH IMPEDANCE
DATA IN DATA OUT
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MODE SELECTION
E H L L W X H L G X L X A15 - A0 (hex) X X X 4E38 B1C7 83E0 7C1F 703F 8B45 4E38 B1C7 83E0 7C1F 703F 4B46 4E38 B1C7 83E0 7C1F 703F 8FC0 4E38 B1C7 83E0 7C1F 703F 4C63 MODE Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Autostore Inhibit Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Autostore inhibit off Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Store Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall I/O Output High Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z POWER Standby Active Active NOTES
L
H
L
Active
k, l, m
L
H
L
Active
k, l, m
L
H
L
Active
k, l, m
lCC
2
L
H
L
Active
k, l, m
Note k: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. Note l: While there are 17 addresses on the STK16CA8, only the lower 16 are used to control software modes. Note m: I/O state depends on the state of G. The I/O table shown assumes G low.
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AutoStorePlusTM/POWER-UP RECALL
NO. 22 23 24 SYMBOLS Standard tRESTORE tSTORE VSWITCH tHLHZ Alternate PARAMETER Power-up RECALL Duration STORE Cycle Duration Low Voltage Trigger Level 2.55
(VCC = 3.0V +20%, -10%)
STK16CA8 MIN MAX 5 10 2.65 UNITS ms ms V NOTES n o
Note n: tRESTORE starts from the time VCC rises above VSWITCH. Note o: If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place.
AutoStorePlusTM/POWER-UP RECALL
VCC 24 VSWITCH
AutoStoreTM 23 tSTORE POWER-UP RECALL 22 tRESTORE W
DQ (DATA OUT)
POWER-UP RECALL
BROWN OUT NO STORE (NO SRAM WRITES)
BROWN OUT AutoStoreTM
BROWN OUT AutoStoreTM RECALL WHEN VCC RETURNS ABOVE VSWITCH
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SOFTWARE-CONTROLLED STORE/RECALL CYCLEp
NO. 25 26 27 28 29 SYMBOLS E cont tAVAV tAVEL tELEH tELAX tRECALL G cont tAVAV tAVGL tGLGH tGLAX tRECALL Alternate tRC tAS tCW PARAMETER STORE/RECALL Initiation Cycle Time Address Set-up Time Clock Pulse Width Address Hold Time RECALL Duration STK16CA8-25 MIN 25 0 20 20 20 MAX
(VCC = 3.0V +20%, -10%)
STK16CA8-35 MIN 35 0 25 20 20 MAX STK16CA8-45 MIN 45 0 30 20 20 MAX UNITS NOTES ns ns ns ns s q
Note p: The software sequence is clocked with E controlled READs or G controlled READs. Note q: The six consecutive addresses must be in the order listed in the Mode Selection Table: (4E38, B1C7, 83E0, 7C1F, 703F, 8FC0) for a STORE cycle or (4E38, B1C7, 83E0, 7C1F, 703F, 4C63) for a RECALL cycle. W must be high during all six consecutive cycles.
SOFTWARE STORE/RECALL CYCLE: E CONTROLLEDq
tAVAV ADDRESS
26 ADDRESS #1 25
tAVAV
ADDRESS #6
25
tAVEL E
tELEH
27
tELAX G
23 29 / tRECALL
28
tSTORE DQ (DATA)
DATA VALID DATA VALID
HIGH IMPEDANCE
SOFTWARE STORE/RECALL CYCLE: G CONTROLLEDq
tAVAV ADDRESS
ADDRESS #1 25
tAVAV
ADDRESS #6
25
E
tAVGL G
26
tGLGH
27
tGLAX DQ (DATA)
DATA VALID DATA VALID
28
tSTORE
23
29 / tRECALL
HIGH IMPEDANCE
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DEVICE OPERATION
The STK16CA8 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as a standard fast static RAM. In nonvolatile mode, data is transferred from SRAM to the nonvolatile elements (the STORE operation) or from the nonvolatile elements to SRAM (the RECALL operation). In this mode SRAM functions are disabled. one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether or not a WRITE operation has taken place.
POWER-UP RECALL
During power up, or after any low-power condition (VCCX < VSWITCH), an internal RECALL request will be latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tRESTORE to complete. If the STK16CA8 is in a WRITE state at the end of power-up RECALL, the WRITE will be inhibited and E or W must be brought high and then low for a write to initiate.
SRAM READ
The STK16CA8 performs a READ cycle whenever E and G are low and W is high. The address specified on pins A0-16 determines which of the 131,072 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until new output data appears or until E or G is brought high, or W is brought low.
SOFTWARE NONVOLATILE STORE
The STK16CA8 software STORE cycle is initiated by executing sequential E controlled READ cycles from six specific address locations. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into nonvolatile memory. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence, or the sequence will be aborted and no STORE or RECALL will take place. To initiate the software STORE cycle, the following READ sequence must be performed:
1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 4E38 (hex) B1C7 (hex) 83E0 (hex) 7C1F (hex) 703F (hex) 8FC0 (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE cycle
SRAM WRITE
A WRITE cycle is performed whenever E and W are low. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low.
AutoStorePlusTM OPERATION
The STK16CA8's automatic STORE on power-down is completely transparent to the system. The AutoStoreTM initiation takes less than 500ns when power is lost (VCC < VSWITCH) at which point the part depends only on its internal capacitor for STORE completion. In order to prevent unneeded STORE operations, automatic STOREs will be ignored unless at least
The software sequence must be clocked with E controlled READs. Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, and it is necessary that G be low for the sequence to be
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valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. sequence has been performed, regardless of device power cycles. The AutoStore Inhibit can be disabled by initiating an AutoStore Inhibit Off sequence. A sequence of read operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore Inhibit Off sequence, the following sequence of E controlled read operations must be performed:
1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 4E38 (hex) B1C7 (hex) 83E0 (hex) 7C1F (hex) 703F (hex) 4B46 (hex) Valid READ Valid READ Valid READ Valid READ Valid READ AutoStore Inhibit Off
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of E controlled READ operations must be performed:
1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 4E38 (hex) B1C7 (hex) 83E0 (hex) 7C1F (hex) 703F (hex) 4C63 (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL cycle
Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation in no way alters the data in the nonvolatile elements. The nonvolatile data can be recalled an unlimited number of times.
LOW AVERAGE ACTIVE POWER
The STK16CA8 draws significantly less current when it is cycled at times longer than 50ns. Figure 3 shows the relationship between ICC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 3.6V, 100% duty cycle on chip enable). Figure 4 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK16CA8 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the Vcc level; and 7) I/O loading.
HARDWARE PROTECT
The STK16CA8 offers hardware protection against inadvertent STORE operation and SRAM WRITEs during low-voltage conditions. When VCCX < VSWITCH, all externally initiated STORE operations and SRAM WRITEs will be inhibited.
PREVENTING STORES
The AutoStoreTM function can be disabled on the fly by initiating an AutoStore Inhibit sequence. A sequence of read operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore Inihibit sequence, the following sequence of E controlled read operations must be performed:
1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 4E38 (hex) B1C7 (hex) 83E0 (hex) 7C1F (hex) 703F (hex) 8B45 (hex) Valid READ Valid READ Valid READ Valid READ Valid READ AutoStore Inhibit
Once the AutoStoreTM inhibit has been initiated, it will remain active until an AutoStoreTM inhibit off
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50 50
Average Active Current (mA)
40
Average Active Current (mA)
40
30
30 TTL CMOS 10
20 TTL 10 CMOS 0 50 100 150 Cycle Time (ns) 200
20
0 50 100 150 Cycle Time (ns) 200
Figure 3: Icc (max) Reads
Figure 4: Icc (max) Writes
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STK16CA8 ORDERING INFORMATION
STK16CA8 - W F 45 I
Temperature Range
Blank = Commercial (0 to 70C) I = Industrial (-40 to 85C)
Access Time
25 = 25ns 35 = 35ns 45 = 45ns
Lead Finish
Blank = 85%Sn/15%Pb F = 100% Sn (Matte Tin)
Package
W = Plastic 32-pin 600 mil DIP
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Document Revision History
Revision 0.0 0.1
Date May 2003 September 2003
Summary Publish new datasheet Added lead-free lead finish
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